amplification apparatus

ABSTRACT

An amplification apparatus comprising first amplification circuitry having first shunt-peak circuitry and second amplification circuitry having second shunt-peak circuitry, wherein the amplification apparatus is arranged to provide an operational bandwidth over which the first and second amplification circuitry amplify signals, and wherein the second shunt-peak circuitry is arranged to use at least part of the first shunt-peak circuitry.

BACKGROUND

The invention relates to an amplification apparatus and a method ofamplification.

A low-noise amplifier for ultra-wideband applications may include twocascaded amplifiers each having a shunt-peak load. As a shunt-peak loadis utilized in the second amplifier, an additional load inductor isneeded, which consumes significant silicon area compared to transistorsand other passive components.

The second stage may omit the inductor, in which case the structuresuffers from a poorer frequency response.

The listing or discussion of a prior-published document in thisspecification should not necessarily be taken as an acknowledgement thatthe document is part of the state of the art or is common generalknowledge.

SUMMARY

According to a first aspect, there is provided an amplificationapparatus comprising

-   -   first amplification circuitry having first shunt-peak circuitry        and second amplification circuitry having second shunt-peak        circuitry, wherein the amplification apparatus is arranged to        provide an operational bandwidth over which the first and second        amplification circuitry amplify signals, and wherein the second        shunt-peak circuitry is arranged to use at least part of the        first shunt-peak circuitry.

The part of the first shunt-peak circuitry used by the second shunt-peakcircuitry may comprise an inductive element.

The first shunt peak circuitry may comprise a first load path having afirst resistive element in series with an inductive element, and thesecond shunt-peak circuitry may comprise a second load path having asecond resistive element in series with the inductive element of thefirst shunt-peak circuitry.

The first and second load paths may be arranged to couple respectiveoutputs of the first and second amplification circuitry to a voltagesupply.

The first shunt-peak circuitry may include a first capacitive elementand the second shunt-peak circuitry may include a second capacitiveelement.

The first capacitive element may be arranged to be in shunt with thefirst load path, and the second capacitive element may be arranged to bein shunt with the second load path.

The first capacitive element may be arranged to couple an output of thefirst amplification circuitry to a voltage supply, and the secondcapacitive element may be arranged to couple an output of the secondamplification circuitry to the voltage supply.

The first amplification circuitry may comprise part of one of a positiveor negative side of a differential amplifier and the secondamplification circuitry may comprise part of the other of the positiveand negative side of the differential amplifier.

According to a second aspect, there is provided a method ofamplification comprising

-   -   using first and second shunt-peak circuitry and first and second        amplification circuitry to provide an operational bandwidth; and    -   using at least part of the first shunt-peak circuitry in the        second shunt-peak circuitry.

According to a third aspect, there is provided an amplificationapparatus comprising

-   -   first means for amplification having first means for        shunt-peaking and second means for amplification having second        means for shunt-peaking, wherein the amplification apparatus is        arranged to provide an operational bandwidth over which the        first and second means for amplification amplify signals, and        wherein the second means for shunt-peaking is arranged to use at        least part of the first means for shunt-peaking.

According to a fourth aspect, there is provided a method ofamplification comprising

-   -   a step for using first and second amplification circuitry and        first and second shunt-peak circuitry to amplify signals over an        operational bandwidth; and    -   a step for using at least part of the first shunt-peak circuitry        in the second shunt-peak circuitry.

The present invention includes one or more aspects, embodiments orfeatures in isolation or in various combinations whether or notspecifically stated (including claimed) in that combination or inisolation.

The above summary is intended to be merely exemplary and non-limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

A description is now given, by way of example only, with reference tothe accompanying drawings, in which:

FIG. 1A shows a circuit diagram of a low-noise amplifier with a resonantload;

FIG. 1B shows an equivalent circuit of the amplifier of FIG. 1A;

FIG. 2 shows an equivalent circuit of an amplifier with a shunt-peakload;

FIG. 3 shows an equivalent circuit of two cascaded amplifiers of thetype shown in FIG. 2;

FIG. 4 shows an equivalent circuit of an amplifier in which a firststage has a shunt-peak load and a second stage has an RC load;

FIG. 5 shows an equivalent circuit of an amplification apparatus with ashared shunt-peak load;

FIG. 6 shows how the voltage gain (in dB) of the amplifiers of FIGS. 2to 5 varies with frequency;

FIG. 7 shows part of FIG. 6 with the voltage gain scaled;

FIG. 8 shows part of FIG. 6 with additional traces for variations inparameters of the amplification apparatus of FIG. 5;

FIG. 9 shows a differential amplification apparatus with a sharedshunt-peak load;

FIG. 10 shows a flowchart representing a method.

DETAILED DESCRIPTION

FIGS. 1A and 1B show an inductively-degenerated low-noise amplifier 10with a resonant load 12.

The resonant load 12 of the low-noise amplifier includes a resistor 14,an inductor 16 and a capacitor 18. The resonant frequency is set by theinductor 16 and the capacitor 18. The −3 dB bandwidth is typically a fewhundred MHz, and depends on the impedance level of the resonant load 12,which is defined by the value of the resistor 14. The bandwidth can beincreased by lowering the value of the resistor 14.

The operational bandwidth of the resonant load 12 is too narrow forwideband applications like ultra wide band (UWB). For that reason, ashunt-peak load 22 shown in FIG. 2 may be used. The shunt-peak load 22includes a first path 24 coupling an output node 26 of the amplifier 20to a voltage supply 28, the first path 24 including a resistor 30 and aninductor 32 connected in series, and a second path 34 coupling theoutput node 26 to the voltage supply 28, the second path 34 including acapacitor 36. The operation of the shunt-peak load 22 is optimized bychoosing appropriate values of the resistor 30 and the inductor 32.

The capacitor 36 represents all the capacitive loading on the outputnode 26. The maximum operational frequency is limited by the pole formedby the resistor 30 and the capacitor 36. The value of the resistor 30cannot be too large in order to avoid degrading the maximum operationalfrequency. Therefore, the impedance level of the shunt-peak load 22 islimited. In modern deep sub-micron CMOS processes, the self-gain of asingle transistor is low. As a result, the voltage gain achieved from asingle amplifier stage with a shunt-peak load 22 is lower than anarrowband amplifier with an RLC resonator, for example. Therefore, asecond amplifier stage is required to achieve adequate gain or signalswing, as shown in FIGS. 3 and 4.

FIG. 3 shows two cascaded amplifiers 20 a, 20 b of the type shown inFIG. 2. As a shunt-peak load 22 b is utilized in the second amplifier 20b, an additional load inductor 32 b is needed, which consumessignificant silicon area compared to transistors and other passivecomponents. The area of the integrated circuit (IC) may be approximatelydouble the area of the integrated circuit for the amplifier 20 of FIG.2.

Alternatively, the second stage may omit the inductor, as shown in FIG.4. This structure suffers from a poorer frequency response than a basicshunt-peak load with similar values of the resistor 30 c and capacitor36 c.

FIG. 5 shows an equivalent circuit of an amplification apparatus 100with a shared shunt-peak load.

The amplification apparatus 100 comprises first amplification circuitry102 having first shunt-peak circuitry 106 and second amplificationcircuitry 104 having second shunt-peak circuitry 108. The first andsecond shunt-peak circuitry 106, 108 are arranged to maximise anoperational bandwidth of the first and second amplification circuitry102, 104.

The first shunt peak circuitry 106 comprises a first load path 110having a first resistive element 112 in series with an inductive element114. The second shunt-peak circuitry 108 comprises a second load path116 having a second resistive element 118 in series with the inductiveelement 114 of the first shunt-peak circuitry 106. The first load path110 is arranged to couple an output 120 of the first amplificationcircuitry 102 to a voltage supply 122. The second load path 116 isarranged to couple an output 124 of the second amplification circuitry104 to the voltage supply 122. The first shunt-peak circuitry 106includes a first capacitive element 126 and the second shunt-peakcircuitry 108 includes a second capacitive element 128. The firstcapacitive element 126 is arranged to be in shunt with the first loadpath 110, and the second capacitive element 128 is arranged to be inshunt with the second load path 116. The first capacitive element 126 isarranged to couple the output 120 of the first amplification circuitry102 to the voltage supply 122, and the second capacitive element 128 isarranged to couple the output 124 of the second amplification circuitry104 to the voltage supply 122.

In this way, the second shunt-peak circuitry 108 is arranged to use theinductive element 114 of the first shunt-peak circuitry 106. This hastwo major benefits. Firstly, the arrangement results in a wideroperational bandwidth and increased gain compared to the single-stageamplifier with a shunt-peak load of FIG. 2. Secondly, an additionalinductor is not required. Thus, the silicon area required by the secondamplifier stage does not significantly increase the overall layout area.

FIG. 6 shows how the voltage gain (in dB) of the amplifiers of FIGS. 2to 5 varies with frequency.

The amplification apparatus 100 of FIG. 5 has a low-frequency pole as isshown in FIG. 6. In addition, there is a zero at higher frequency, whichcancels the effect of the low-frequency pole and leads to a flat gainresponse at a specific frequency area of several GHz.

The flat area particularly extends the bandwidth compared to that of asingle-stage amplifier with a shunt-peak load, like the amplifier shownin FIG. 2. An increase in gain is also achieved. Because the physicalsize of the transistors and resistors of the second amplifier stage aresignificantly smaller than the layout size of an inductor, thegain/bandwidth improvement is achieved without penalty of significantincrease in layout area.

Compared to the amplifiers of FIGS. 3 and 4, the amplification apparatus100 provides lower gain at high frequencies with identical componentvalues, as is shown in FIG. 6. When the gain responses of the amplifiersof FIGS. 2 to 5 are scaled to 0 dB at the band of interest, theamplification apparatus 100 has the highest −3 dB cut-off frequency, asshown in FIG. 7. In addition, the high-pass frequency of theamplification apparatus 100 can be traded for higher gain at the flatfrequency area by increasing the values of the resistive elements 112,118, as shown in FIG. 8. Furthermore, if the gains (g_(m)) of the firstand second amplification circuitry 102, 104 are increased, both the gainand bandwidth are increased.

Thus, the amplification apparatus 100 provides improved overallperformance of an amplifier in a case in which wide operationalbandwidth is required but the number of on-chip inductors may not beincreased.

FIG. 9 shows a differential amplification apparatus 200 with a sharedshunt-peak load. The apparatus 200 includes a positive side 202 and anegative side 204.

The positive side 202 includes amplification circuitry 206, firstshunt-peak circuitry 208 and second shunt-peak circuitry 210. The firstshunt-peak circuitry 208 includes a resistive element 212 in series withan inductive element 214. The second shunt-peak circuitry 210 includes aresistive element 216 and a capacitive element 218. The resistiveelement 216 of the second shunt-peak circuitry 210 is coupled to aninductive element 219 of the first shunt-peak circuitry 220 of thenegative side 204.

The negative side 204 includes amplification circuitry 222, firstshunt-peak circuitry 224 and second shunt-peak circuitry 226. The firstshunt-peak circuitry 224 includes a resistive element 228 in series withthe inductive element 219. The second shunt-peak circuitry 226 includesa resistive element 228 and a capacitive element 230. The resistiveelement 228 of the second shunt-peak circuitry 226 is coupled to theinductive element 214 of the first shunt-peak circuitry 206 of thepositive side 202.

The amplification apparatus 200 is intended for use as a localoscillator buffer in an ultra-wideband receiver. Because of a 180-degreephase shift between the positive and negative sides, the shunt-peakcircuitry of the positive side is cross-connected to the shunt-peakcircuitry of the negative side.

In a variant, the two inductive elements 214, 218 may be part of asingle differential inductor.

FIG. 10 shows a flowchart representing a method of amplificationcomprising (1002) using first shunt-peak circuitry and second shunt-peakcircuitry to maximise an operational bandwidth of first amplificationcircuitry and second amplification circuitry, and (1004) using at leastpart of the first shunt-peak circuitry in the second shunt-peakcircuitry.

The invention is applicable to radio receivers, integrated circuits,low-noise amplifiers, buffers, and applications with widebandoperational bandwidth, for example wideband code division multipleaccess (WCDMA), ultra-wideband (UWB) and wireless local area network(WLAN) systems. It should be noted that the invention is not limitedonly to complementary metal oxide silicon (CMOS) low-noise amplifiers,and can be utilized in all two-stage amplifiers, for example localoscillator (LO) buffers and various semiconductor technologies, forexample, in bipolar junction transistor (BJT) technology.

It will be appreciated that the aforementioned circuitry may have otherfunctions in addition to the mentioned functions, and that thesefunctions may be performed by the same circuit.

The applicant hereby discloses in isolation each individual featuredescribed herein and any combination of two or more such features, tothe extent that such features or combinations are capable of beingcarried out based on the present specification as a whole in the lightof the common general knowledge of a person skilled in the art,irrespective of whether such features or combinations of features solveany problems disclosed herein, and without limitation to the scope ofthe claims. The applicant indicates that aspects of the presentinvention may consist of any such individual feature or combination offeatures. In view of the foregoing description it will be evident to aperson skilled in the art that various modifications may be made withinthe scope of the invention.

While there have been shown and described and pointed out fundamentalnovel features of the invention as applied to preferred embodimentsthereof, it will be understood that various omissions and substitutionsand changes in the form and details of the devices and methods describedmay be made by those skilled in the art without departing from thespirit of the invention. For example, it is expressly intended that allcombinations of those elements and/or method steps which performsubstantially the same function in substantially the same way to achievethe same results are within the scope of the invention. Moreover, itshould be recognized that structures and/or elements and/or method stepsshown and/or described in connection with any disclosed form orembodiment of the invention may be incorporated in any other disclosedor described or suggested form or embodiment as a general matter ofdesign choice. It is the intention, therefore, to be limited only asindicated by the scope of the claims appended hereto. Furthermore, inthe claims means-plus-function clauses are intended to cover thestructures described herein as performing the recited function and notonly structural equivalents, but also equivalent structures. Thusalthough a nail and a screw may not be structural equivalents in that anail employs a cylindrical surface to secure wooden parts together,whereas a screw employs a helical surface, in the environment offastening wooden parts, a nail and a screw may be equivalent structures.

1. An apparatus comprising first amplification circuitry having firstshunt-peak circuitry and second amplification circuitry having secondshunt-peak circuitry, wherein the second shunt-peak circuitry isarranged to use at least part of the first shunt-peak circuitry andwherein the first shunt-peak circuitry comprises a first load pathhaving a first resistive element in series with an inductive element,and wherein the second shunt-peak circuitry comprises a second load pathhaving a second resistive element in series with the inductive elementof the first shunt-peak circuitry. 2-11. (canceled)
 12. The apparatus ofclaim 1 wherein the first and second load paths are arranged to couplerespective outputs of the first and second amplification circuitry to avoltage supply.
 13. The apparatus of claim 1 wherein the firstshunt-peak circuitry comprises a first capacitive element and the secondshunt-peak circuitry comprises a second capacitive element.
 14. Theapparatus of claim 13 wherein the first capacitive element is arrangedto be in shunt with the first load path, and the second capacitiveelement is arranged to be in shunt with the second load path.
 15. Theapparatus of claim 13 wherein the first capacitive element is arrangedto couple an output of the first amplification circuitry to a voltagesupply, and the second capacitive element is arranged to couple anoutput of the second amplification circuitry to the voltage supply. 16.The apparatus of claim 1 wherein the first amplification circuitrycomprises part of one of a positive or negative side of a differentialamplifier and the second amplification circuitry comprises part of theother of the positive and negative side of the differential amplifier.17. A method comprising: using first and second amplification circuitryand first and second shunt-peak circuitry to amplify signals; using atleast part of the first shunt-peak circuitry in the second shunt-peakcircuitry, the first shunt-peak circuitry comprising a first load pathhaving a first resistive element in series with an inductive element,and the second shunt-peak circuitry comprising a second load path havinga second resistive element in series with the inductive element of thefirst shunt-peak circuitry.
 18. The method of claim 17 wherein the firstand second load paths are arranged to couple respective outputs of thefirst and second amplification circuitry to a voltage supply.
 19. Themethod of claim 17 wherein the first shunt-peak circuitry comprises afirst capacitive element and the second shunt-peak circuitry comprises asecond capacitive element.
 20. The method of claim 19 wherein the firstcapacitive element is arranged to be in shunt with the first load path,and the second capacitive element is arranged to be in shunt with thesecond load path.
 21. The method of claim 19 wherein the firstcapacitive element is arranged to couple an output of the firstamplification circuitry to a voltage supply, and the second capacitiveelement is arranged to couple an output of the second amplificationcircuitry to the voltage supply.
 22. An apparatus comprising: firstmeans for amplification having first means for shunt-peaking; and secondmeans for amplification having second means for shunt-peaking, whereinthe second means for shunt-peaking is arranged to use at least part ofthe first means for shunt-peaking, and wherein the first means forshunt-peaking comprises a first load path means having a first resistivemeans in series with an inductive means, and wherein the second meansfor shunt-peaking comprises a second load path means having a secondresistive means in series with the inductive means of the first meansfor shunt-peaking.
 23. A method comprising: a step for using first andsecond amplification circuitry and first and second shunt-peak circuitryto amplify signals over an operational bandwidth; and a step for usingat least part of the first shunt-peak circuitry in the second shunt-peakcircuitry, the first shunt-peak circuitry comprising a first load pathhaving a first resistive element in series with an inductive element,and the second shunt-peak circuitry comprising a second load path havinga second resistive element in series with the inductive element of thefirst shunt-peak circuitry.